insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was moved inside a function in Xen. This code movement missed a variable changing meaning / value between old and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition, omitting flushes where such are necessary.
Published 2022-07-26 13:15:10
Updated 2022-12-12 20:45:37
Source Xen Project
View at NVD,   CVE.org

Products affected by CVE-2022-33745

Exploit prediction scoring system (EPSS) score for CVE-2022-33745

0.04%
Probability of exploitation activity in the next 30 days EPSS Score History
~ 11 %
Percentile, the proportion of vulnerabilities that are scored at or less

CVSS scores for CVE-2022-33745

Base Score Base Severity CVSS Vector Exploitability Score Impact Score Score Source First Seen
8.8
HIGH CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H
2.0
6.0
NIST

References for CVE-2022-33745

Jump to
This web site uses cookies for managing your session, storing preferences, website analytics and additional purposes described in our privacy policy.
By using this web site you are agreeing to CVEdetails.com terms of use!