CVE-2020-0574 : Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to poten

Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.

Published 2020-03-12 21:15:14

Updated 2021-07-21 11:39:24

Source Intel Corporation

View at NVD, CVE.org

Vulnerability category: Information leak

Exploit prediction scoring system (EPSS) score for CVE-2020-0574

EPSS FAQ

0.04%

Probability of exploitation activity in the next 30 days EPSS Score History

~ 10 %

Percentile, the proportion of vulnerabilities that are scored at or less

CVSS scores for CVE-2020-0574

Base Score	Base Severity	CVSS Vector	Exploitability Score	Impact Score	Score Source
3.6	LOW	AV:L/AC:L/Au:N/C:P/I:P/A:N	3.9	4.9	NIST
Access Vector: Local Access Complexity: Low Authentication: None Confidentiality Impact: Partial Integrity Impact: Partial Availability Impact: None
5.9	MEDIUM	CVSS:3.1/AV:P/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:N	0.7	5.2	NIST
Attack Vector: Physical Attack Complexity: Low Privileges Required: Low User Interaction: None Scope: Unchanged Confidentiality: High Integrity: High Availability: None

Products affected by CVE-2020-0574

Intel » Max 10 Fpga Firmware
cpe:2.3:o:intel:max_10_fpga_firmware:*:*:*:*:*:*:*:*
Matching versions
When used together with: Intel » Max 10 Fpga » Version: N/A

Vulnerability Details : CVE-2020-0574

Exploit prediction scoring system (EPSS) score for CVE-2020-0574

CVSS scores for CVE-2020-0574

References for CVE-2020-0574

Products affected by CVE-2020-0574