Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
Published 2024-08-14 13:45:32
Updated 2024-08-14 17:49:14
View at NVD,   CVE.org

Products affected by CVE-2024-24853

Please log in to view affected product information.

Exploit prediction scoring system (EPSS) score for CVE-2024-24853

0.02%
Probability of exploitation activity in the next 30 days EPSS Score History
~ 2 %
Percentile, the proportion of vulnerabilities that are scored at or less

CVSS scores for CVE-2024-24853

Base Score Base Severity CVSS Vector Exploitability Score Impact Score Score Source First Seen
7.2
HIGH CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H
N/A
N/A
Intel Corporation 2024-08-14
7.2
HIGH CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H
0.6
6.0
Intel Corporation 2024-08-14
7.3
HIGH CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/V...
N/A
N/A
Intel Corporation 2024-08-14
7.3
HIGH CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/V...
N/A
N/A
Intel Corporation 2024-08-14

CWE ids for CVE-2024-24853

  • The product performs multiple related behaviors, but the behaviors are performed in the wrong order in ways which may produce resultant weaknesses.
    Assigned by:
    • 6dda929c-bb53-4a77-a76d-48e79601a1ce (Primary)
    • secure@intel.com (Secondary)
Jump to
This web site uses cookies for managing your session, storing preferences, website analytics and additional purposes described in our privacy policy.
By using this web site you are agreeing to CVEdetails.com terms of use!