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insufficient TLB flush for x86 PV guests in shadow mode For migration as well as to work around kernels unaware of L1TF (see XSA-273), PV guests may be run in shadow paging mode. To address XSA-401, code was moved inside a function in Xen. This code movement missed a variable changing meaning / value between old and new code positions. The now wrong use of the variable did lead to a wrong TLB flush condition, omitting flushes where such are necessary.
Publish Date : 2022-07-26 Last Update Date : 2022-12-12
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CVSS Scores & Vulnerability Types
| CVSS Score |
0.0 |
| Confidentiality Impact |
??? |
| Integrity Impact |
??? |
| Availability Impact |
??? |
| Access Complexity |
??? |
| Authentication |
??? |
| Gained Access |
None |
| Vulnerability Type(s) |
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| CWE ID |
CWE id is not defined for this vulnerability |
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Products Affected By CVE-2022-33745
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Number Of Affected Versions By Product
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References For CVE-2022-33745
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Metasploit Modules Related To CVE-2022-33745
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